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important question for anyone good at x86. can microcode cache the top of the stack in processor registers for sufficiently nearby pushes and pops or do stack accesses always require a cache access no matter what
@mothcompute idk if there are additional microarchitectural register caches for stack values, but I know on Intel there's some caching of past stack values as part of IBP for speculating returns. when you reach a RET the Return Stack Buffer (RSB) contains the target prediction for speculative execution beyond that point, and when the stack pop comes back (from cache hit or memory fetch) it can either confirm successful prediction or rewind.
@mothcompute there may also be some cleverness with writeback coalescing on temporally grouped stack ops, but I'd bet they at least go as far as L1 each time otherwise coherence would be a mess. (this is mostly an educated guess though and I am prepared to be surprised)
@gsuberland @mothcompute yeh it will have to get to L1 eventually, but x86 explicitly allows ordering to be broken by forwarding within the processor that did the store, so it's a bit weaker (I came across this a while back because it makes emulating architectures with stronger ordering on x86 tricky). see 'Intra-Processor Forwarding Is Allowed'
(8.2.3.5 in my copy of the SDM)